Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in a liquid carrier and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. U.S. Pat. No. 5,527,423, for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface with a polishing slurry comprising high purity fine metal oxide particles in an aqueous medium. Polishing compositions are typically used in conjunction with polishing pads (e.g., a polishing cloth or disk). Suitable polishing pads are described in U.S. Pat. Nos. 6,062,968, 6,117,000, and 6,126,532, which disclose the use of sintered polyurethane polishing pads having an open-celled porous network, and U.S. Pat. No. 5,489,233, which discloses the use of solid polishing pads having a surface texture or pattern. Instead of, or in addition to, being suspended in the polishing composition, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,958,794 discloses a fixed abrasive polishing pad.
As a method for isolating elements of a semiconductor device, a great deal of attention is being directed towards a shallow trench isolation (STI) process where a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer (e.g., an oxide) is deposited to fill the trenches. Due to variation in the depth of trenches, or lines, formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches. The excess dielectric material is then typically removed by a chemical-mechanical planarization process to expose the silicon nitride layer. When the silicon nitride layer is exposed, the largest area of the substrate exposed to the chemical-mechanical polishing composition comprises silicon nitride, which must then be polished to achieve a highly planar and uniform surface.
Generally, past practice has been to emphasize selectivity for oxide polishing in preference to silicon nitride polishing. Thus, the silicon nitride layer has served as a stopping layer during the chemical-mechanical planarization process, as the overall polishing rate decreased upon exposure of the silicon nitride layer. For example, U.S. Pat. No. 6,544,892 and references cited therein describe polishing compositions which provide selectivity of silicon dioxide to silicon nitride. Also, U.S. Pat. No. 6,376,381 describes the use of certain nonionic surfactants to increase the polishing selectivity between silicon oxide and silicon nitride layers.
Recently, selectivity for oxide polishing in preference to polysilicon polishing has also been emphasized. For example, the addition of a series of BRIJ™ and polyethylene oxide surfactants, as well as PLURONIC™ L-64, an ethylene oxide-propylene oxide-ethylene oxide triblock copolymer with an HLB of 15, is purported to increase the polishing selectivity of oxide to polysilicon (see Lee et al., “Effects of Nonionic Surfactants on Oxide-to-Polysilicon Selectivity during Chemical Mechanical Polishing,”. J. Electrochem. Soc., 149(8): G477-G481 (2002)). Also, U.S. Pat. No. 6,626,968 purports to obtain polishing selectivity of silicon oxide to polysilicon through the use of a polymer additive having hydrophilic and hydrophobic functional groups selected from polyvinylmethylether, polyethylene glycol, polyoxyethylene 23 lauryl ether, polypropanoic acid, polyacrylic acid, and polyether glycol bis(ether).
The STI substrate is typically polished using a conventional polishing medium and an abrasive-containing polishing slurry. However, polishing STI substrates with conventional polishing media and abrasive-containing polishing slurries has been observed to result in overpolishing of the substrate surface or the formation of recesses in the STI features and other topographical defects such as microscratches on the substrate surface. This phenomenon of overpolishing and forming recesses in the STI features is referred to as dishing. Dishing is also used to refer to overpolishing and forming recesses in other types of features. Dishing is undesirable because dishing of substrate features may detrimentally affect device fabrication by causing failure of isolation of transistors and transistor components from one another, resulting in short-circuits. Additionally, overpolishing of the substrate may also result in oxide loss and exposure of the underlying oxide to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
Despite these polishing compositions and methods, there remains a need in the art for polishing compositions and methods that can provide desirable selectivity of silicon oxide, silicon nitride, and polysilicon and that have suitable removal rates, low defectivity, and suitable dishing performance. The invention provides such a composition and method. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.